Espressif Systems /ESP32-S2 /SPI0 /LCD_D_MODE

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Interpret as LCD_D_MODE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0D_DQS_MODE 0D_CD_MODE 0D_DE_MODE 0D_HSYNC_MODE 0D_VSYNC_MODE 0 (DE_IDLE_POL)DE_IDLE_POL 0 (HS_BLANK_EN)HS_BLANK_EN

Description

LCD delay number

Fields

D_DQS_MODE

the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

D_CD_MODE

the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

D_DE_MODE

the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

D_HSYNC_MODE

the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

D_VSYNC_MODE

the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

DE_IDLE_POL

It is the idle value of spi_de.

HS_BLANK_EN

1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.

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